Plasma display panels are presently in commercial use as digitally addressable information display devices. The panel itself typically consists of two glass plates with a gas mixture sealed between them. A plurality of X-axis electrodes extend in a mutually parallel array on an interior substrate of one plate, and a plurality of Y-axis electrodes extending in a mutually parallel array on the interior of the other plate. The X-axis electrodes are at a 90.degree. angle to the Y-axis electrodes, thereby forming a plurality of intersections between the X-axis and Y-axis electrodes. A typical commercially available AC plasma panel has 512 X-axis electrodes and 512 Y-axis electrodes, yielding 262,144 intersections, or cells.
When a voltage of between 180 to 200 volts is applied across an X-axis electrode and a Y-axis electrode, a discharge in the gas occurs at the cell formed by the electrodes, causing a pulse of light to be emitted at this point. Simultaneously, a charge is collected on the cell wall, which results in the cell being an "on" cell. Once such a discharge has been produced and the cell is turned "on", the collected wall charge acts to continue the discharging when a lesser AC sustain voltage is applied between the electrodes. In an "on" cell, the gas will discharge and the cell will emit a pulse of light at each transition of the applied AC sustain waveform. The sustain voltage, however, is insufficient to initiate a discharge at an X-Y intersection. This phenomenon is known as inherent memory, and was originally disclosed by Baker et al, U.S. Pat. No. 3,499,167, and by Bitzer et al, in U.S. Pat. No. 3,959,190. By precisely timing, shaping, and phasing multiple alternating voltage waveforms supplied to X and Y axes electrodes, the generation, sustaining and erasure of light emitting gas discharges at selected locations on the plasma display panel can be controlled.
Four functions are used to control the operation of an AC plasma panel: the write function, the erase function, the sustain function, and the bulk-erase function. The write function causes a selected cell on the panel to change from the "off", or non-light emitting state, to the "on" or light emitting state. The sustain function maintains the state of all cells on the panel, i.e. causes "on" cells to remain on, and "off" cells to remain off. The sustain function also causes the "on" cells to emit light. The erase function causes a selected cell to be changed from the "on" state to the "off" state. The bulk-erase function causes all "on" cells in the panel simultaneously to be changed to the "off" state.
Operation of the write, erase, sustain, and bulk-erase functions is generally controlled by four logic signals: the X-sustain signal XS, the Y-sustain signal YS, the X-address pulse XAP, and the Y-address pulse YAP. These signals, generally supplied by a waveform ROM (Read Only Memory), are digital pulse trains typically recurring at a frequency of 50 kHz. The logic signals are supplied to the sustain and drive circuits, and cause the circuits to execute the four control functions on the panel. Since the typical operational frequency of the plasma display system is 50 kHz, the complex waveform for each of the four control functions is executed in a 20 microsecond period. It has been found necessary, in the prior art, to have all four functions of an equal length since one ROM is used to store them, and addressing is less complex for the constant length.
This 20 microsecond period is a compromise, since the amount of time needed for the various operations varies. For example, the amount of time needed for a sustain cycle is about 15 microseconds, for a write cycle about 23 microseconds, for an erase cycle about 16 microseconds, and for a bulk-erase cycle only about 8 microseconds. The typical 20 microsecond period is, therefore, a compromise for the four control functions. Increasing the period for each of the four functions to the 23 microseconds taken by the write function would increase the stability of the plasma display panel after a write function, but it would cause the system to be approximately 15% slower due to the longer period of time required to perform each function. The 20 microsecond period decreases the stability of the plasma display panel after a write function somewhat, an acceptable compromise.
A more significant problem is the fact that prior art systems bear the constraint of having a fixed time base, this fixed time base allowing only one fixed cycle length of 20 microseconds. If the lengths of the four control functions could differ, each of the functions could be done in the minimal time required, thus yielding both a higher data rate and a better write function.
It is also desirable to be able to add a new function which has a length greater than the fixed cycle length of 20 microseconds, such as the distributed conditioning pulse, which is the subject of copending U.S. patent application Ser. No. 273,093, filed on June 12, 1981, entitled: Distributed Conditioning For An AC Plasma Panel, by Joseph T. Suste and Michael J. Marentic. Since the distributed conditioning function takes more than 20 microseconds to perform, two 20 microsecond periods must be chained together to give a compound mode of length 40 microseconds. In order to perform the operation, extra logic for the ROM address lines is necessary to execute the two 20 microsecond component periods sequentially. It may be desirable to have other functions which also take a greater length than the standard 20 microsecond period. Therefore, it may be seen that the use of a fixed time base having a 20 microsecond period does not allow sufficient flexibility to operate sophisticated plasma display systems.
One possible solution is to increase the length of the period. This solution presents several problems of its own. First, the maximum update rate would be reduced by an amount directly proportional to the increase in the period of the cycle. Also, if only one sustain cycle is run in the increased period, the brightness of the display would be reduced, since only two pulses of light would be emitted from the display in the increased period.
Another major problem caused by the fixed 20 microsecond time base is that large scale parallel addressing is not possible. It is highly desirable to address an entire line, comprised of the 512 cells along an X-electrode, simultaneously. However, the time required to load the data necessary to address 512 cells is at least 71 microseconds to prepare the drive circuitry for a write or erase operation. Five complete sustain operations can be done in a period of 75 microseconds, providing sufficient time for loading data. A write function, done properly, takes 23 microseconds, so it may be seen that a period of approximately 98 microseconds or more is required in order to parallel address 512 cells. If a fixed period of 100 microseconds is adopted, 512 cell parallel addressing would be possible, but at a substantial cost. Since the sustain and bulk-erase cycles would have the same period, to prevent complex addressing circuitry from being required, there would be a substantial delay in addressing, i.e. performing write or erase operations, if a sustain function was being executed at the time.
A major consideration in the design of plasma display panel systems is the amount of ROM memory storage space required, since larger amounts of memory increase both the cost and complexity of the system. The basic system described above, with only write, erase, sustain, and bulk-erase functions, at a fixed 20 microsecond period, needs only about 1K of memory.
If another function is to be added to the system, the amount of required memory is doubled. For a complex function, such as distributed conditioning, described in the above-referenced copending patent application, to be added to the system, the memory space in the ROM must be quadrupled, and external control logic must be added to access these new locations in the ROM.
If 512 cell parallel addressing is desired, the minimum period for a cycle that would allow 512 cell parallel addressing is about 100 microseconds. Each of the pulse trains stored in the ROM would have to be 100 microseconds long, 5 times the length of the basic system. Therefore, in order to add a 512 cell parallel addressing feature to the basic plasma panel system, the memory required would be 5 times the minimum memory of 1K, since the address groups are 5 times as long as the previous 20 microseconds, and thus 5K of memory would be required. If it is desired to parallel address 512 cell locations, and to also have a distributed conditioning feature, the memory capability must be further expanded.
Another desirable feature in a plasma panel is brightness control. The addition of brightness control expands the ROM by a factor equal to the number of brightness levels desired, typically 8. If brightness control is desired in a system with more than the basic four control functions, and 512 cell parallel addressing is also desired, the amount of memory required becomes prohibitively large, as demonstrated by the following example. For a system with 8 different control functions and 8 brightness levels, with a 120 microsecond period (required for 8 level brightness control), the amount of memory required is 384 address.times.8 modes.times.8 brightness levels.times.5 outputs (required for distributed conditioning)=120K. This size of memory is simply too expensive to be considered. Thus, if it is desired to have constant data rate brightness control in combination with sophisticated operating modes, an alternative system is required.